GlobalFoundries Details FDX Fusion, a Planar 7nm-Class Process Without EUV
Target volume production is 2030, with commercial production planned for 2028 and a focus on connectivity, radar and edge chips.
GlobalFoundries is working on FDX Fusion, an FD-SOI process that its vice president Sudipto Bose says can reach 7nm-class performance using planar transistors and DUV lithography rather than EUV. The company says the process would offer roughly 8nm-class logic density and cut design and manufacturing costs relative to FinFET nodes, with transistor density still below 7nm-class FinFET parts. Bose reports that FDX Fusion should deliver about 500 GHz fT/fmax and roughly 2.2 times the digital gate density of the current 22FDX generation. He names connectivity, automotive radar, edge MCUs with inference and data-center signal paths as target markets. Commercial production is planned for 2028, with high-volume manufacturing targeted for 2030.
Why it matters
The process aims to bring 7nm-class performance using planar transistors and DUV lithography instead of EUV tools, which could make advanced chip production an option for a wider range of manufacturers. Its targeted markets, including connectivity, automotive radar, edge microcontrollers and data-center signal paths, are areas where cost and performance both matter. Transistor density would still sit below that of 7nm-class FinFET parts, so the trade-off is cost and simplicity against raw density.
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